`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:15:08 02/24/2014
// Design Name:   top_level
// Module Name:   /home/choosegoose/code/predator-vision/integration_tb.v
// Project Name:  pseudo_with_clocking
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: top_level
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module integration_tb;

	// Inputs
	reg cam_clk;
	reg clk_in;
	reg frame_valid;
	reg line_valid;
	reg [2:0] switch;
	reg [7:0] pixel_data;

	// Outputs
	wire [7:0] test_pixel_data;
	wire [3:0] ext_tmds;
	wire [3:0] ext_tmdsb;
	wire [3:0] hmd_tmds;
	wire [3:0] hmd_tmdsb;
	wire [7:0] cc_output_data_r;
	wire [7:0] cc_output_data_g;
	wire [7:0] cc_output_data_b;	 

	// Instantiate the Unit Under Test (UUT)
	top_level uut (
		.cam_clk(cam_clk), 
		.clk_in(clk_in), 
		.frame_valid(frame_valid), 
		.line_valid(line_valid), 
		.switch(switch), 
		.pixel_data(pixel_data), 
		.test_pixel_data(test_pixel_data), 
		.ext_tmds(ext_tmds), 
		.ext_tmdsb(ext_tmdsb), 
		.hmd_tmds(hmd_tmds), 
		.hmd_tmdsb(hmd_tmdsb),
		.cc_output_data_r(cc_output_data_r),
		.cc_output_data_g(cc_output_data_g),
		.cc_output_data_b(cc_output_data_b)
	);

	initial begin
		// Initialize Inputs
		cam_clk = 0;
		clk_in = 0;
		frame_valid = 8'd1;
		line_valid = 8'd1;
		pixel_data = 8'd0;
		switch = 3'b001;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
	
	// Add stimulus here
		always begin
			//#10 line_valid = ~line_valid;
			#5 cam_clk = ~cam_clk;
			#5 clk_in = ~clk_in;
		end
		
		initial begin
      pixel_data <= 8'd111; //test for Y = 15
		$monitor("pixel_data = %d , pixel_data [3:0] = %b", pixel_data, pixel_data [3:0] ); 
		$monitor("ext_tmds = %b, ext_tmds = %b, hmd_tmds = %b, hmd_tmdsb = %b", ext_tmds, ext_tmdsb, hmd_tmds, hmd_tmdsb);
		#14 pixel_data <= 8'd142; //test for Y = 14
		$monitor("pixel_data = %d , pixel_data [3:0] = %b", pixel_data, pixel_data [3:0] ); 
		$monitor("ext_tmds = %b, ext_tmds = %b, hmd_tmds = %b, hmd_tmdsb = %b", ext_tmds, ext_tmdsb, hmd_tmds, hmd_tmdsb);
		#10 $finish;
	end
      
endmodule

